一种有源零点补偿的片上LDO设计  

Design of an On-Chip LDO with Active Zero Compensation

作　　者：胡云斌[1,2] 周勇[2,3] 胡永贵[4] 顾宇晴 

机构地区：[1]重庆邮电大学,重庆400065 [2]模拟集成电路重点实验室,重庆400060 [3]重庆大学,重庆400044 [4]中国电子科技集团公司第二十四研究所,重庆400060 [5]西安交通大学,西安710049

出　　处：《微电子学》2017年第3期326-329,共4页Microelectronics

摘　　要：提出了一种新颖的有源零点补偿LDO结构,实现了LDO在全负载范围内的稳定,1~10 MHz范围内的电源抑制比提高了10dB。采用欠冲电压减小技术,显著减小了输出欠冲电压,提高了瞬态响应性能。基于SMIC 65nm CMOS工艺,设计了输出电压为1V、压差电压为200mV、最大输出电流为100mA的无片外电容LDO。仿真结果显示,空载时LDO的相位裕度为64.3°,最大过冲和欠冲电压分别为52mV和47mV,满载时LDO的电源抑制比为-66dB@10kHz。A novel LDO structure with active zero compensation was firstly presented. Based on this kind of structure, the proposed LDO was stable within full load range, and the PSRR was improved by 10 dB in the critical worst range of 1-10 MHz. Using the undershoot reduction technology, the undershoot voltage was reduced significantly, and the transient performance was improved. Based on SMIC 65 nm CMOS process, an on-chip LDO with 1 V output voltage, 200 mV dropout voltage, and 100 mA maximum load current was designed. Simulation results showed that the proposed LDO could achieve 64.3° phase margin in no load condition, and the maximum overshoot and undershoot voltage was 52 mV and 47 mV respectively. The PSRR was -66 dB@10 kHz in full load condition.

关 键 词：低压差线性稳压器 有源零点补偿 无片外电容 电源抑制比 

分 类 号：TN432[电子电信—微电子学与固体电子学]