6.25Gb/s串行数据接收器设计  

Design of 6.25 Gb/s SerDes Receiver

作　　者：田啸[1] 何燕冬[1] 

机构地区：[1]北京大学微电子研究院,北京100871

出　　处：《微电子学与计算机》2017年第7期119-122,共4页Microelectronics & Computer

摘　　要：设计一款基于65nm CMOS工艺、数据传输速率在6.25Gb/s的SerDes接收器,其中均衡电路采用连续时间线性均衡器;采样电路采用了一种新型灵敏放大器,较传统结构将灵敏度提升了一个量级,同时解决了传统结构输出信号下降沿比上升沿慢一个门延迟的问题;时钟数据恢复电路(CDR)采用半速率采样二阶CDR系统实现.通过仿真验证,该接收器具有正确逻辑功能,功耗为10.2mW.In this paper, a 65 nm CMOS 6. 25 Gb/s SerDes receiver is designed. Equalization is achieved by using continuous-time linear equalizer. The sampler employs a novel sense amplifier（SA）, which improves the sensitivity by the conventional SA of magnitude and simultaneously solves the problem that falling edge lags rising edge the time of a gate delay; a half-rate second order clock and data recovery system is presented. Simulation results show that the receiver has the correct logic function, the power consumption is 10. 2 mW.

关 键 词：高速串行 接收器 灵敏放大器 

分 类 号：TN43[电子电信—微电子学与固体电子学]