基于有限状态机的多周期CPU实验设计  

Design of multi-period CPU experiment based on finite state machine

作　　者：冯建文[1] 

机构地区：[1]杭州电子科技大学计算机学院,浙江杭州310018

出　　处：《实验技术与管理》2017年第7期127-131,共5页Experimental Technology and Management

基　　金：教育部国家精品资源共享课程"计算机组成原理";浙江省教育技术研究规划课题(JA007)

摘　　要：设计了一个基于FPGA的多周期CPU实验,并将有限状态机应用于模型计算机的设计与实现。模型计算机基于MIPS处理器,含8条典型指令。给出了多周期CPU的数据通路与指令流程图,并按照有限状态机的设计方法,完成了状态转移图的设计和HDL的程序描述。实验不仅使学生掌握有限状态机这一重要的数字系统设计工具,同时也有助于学生加深理解"计算机就是一个有限状态机"的概念。在课程实践应用中教学效果良好。A multi-period CPU experiment based on FPGA is designed,and the finite state machine is designed and applied to the model computer.The model computer is based on MIPS processor with 8 typical instructions.The data path and instruction flow chart of multi-period CPU are presented,and according to the design method of the finite state machine,the state transition diagram and the program description of HDL are completed.The experiment helps the students not only to grasp the important digital system design tool of the finite state machine,but also to understand the concept that＂Computer is a finite state machine.＂In practice,the teaching effect is fine.

关 键 词：多周期CPU 有限状态机 实验设计 FPGA 

分 类 号：G642[文化科学—高等教育学] TP3-4[文化科学—教育学]