VHDL语言逻辑综合的研究  

The research in the logic synthesis of VHDL language

作　　者：刘新云[1] 熊国海[2] 

机构地区：[1]华中科技大学材料科学与工程学院,武汉430074 [2]三峡大学电气学院,湖北宜昌443002

出　　处：《电测与仪表》2002年第8期36-38,57,共4页Electrical Measurement & Instrumentation

摘　　要：VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。本文对VHDL语言综合进程作了详细的讨论,认为综合过程就是将RTL级描述、对设计的电路约束和属性及工艺库这些输入产生一个优化的门级网表。The logic synthesis of VHDL language is a method that t he description of higher abstract hierarchy is shifted to lower one automatically .In this paper,the pro-cess of VHDL language synthesized is discussed in deta il.It is thought that process synthesized is that the RTL gradation descriptio n,the circuit restriction designed,prop-erty and technology bank are input a nd then a gate gradation netlist optimized will be gained.

关 键 词：VHDL 逻辑综合 描述 

分 类 号：TP312[自动化与计算机技术—计算机软件与理论]