用于特征提取的小尺寸事件型卷积处理器  

A small Size Event-Based Convolution Processor for Feature Extraction

作　　者：卢成业 高志远[1] 徐江涛[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《传感技术学报》2017年第4期535-541,共7页Chinese Journal of Sensors and Actuators

基　　金：国家自然科学基金项目(61604107;61434004)

摘　　要：设计了一款用于动态视觉传感器数据特征提取的小尺寸事件型卷积处理器,该卷积处理器包含了32×32的累加阵列、用于存储卷积核的RAM阵列、左/右移位模块、控制模块和异步的事件读出模块。为了减小面积,设计了2 bit的32×32的RAM阵列来存储所需的卷积核;在累加阵列中,采用7 bit的二进制计数器代替传统的加法器来实现卷积核的累加操作,在0.18μm CMOS工艺下,每个卷积单元的面积为37.5μm×40μm,对于每个事件输入输出的最小延时为17 ns,能够处理的最大事件率为12.5 Meps。基于该卷积处理器搭建了一个识别系统,利用16个卷积处理器来提取特征,利用脉冲神经网络实现了分类识别。实验结果表明,使用2 bit卷积核的小尺寸卷积处理器能够准确完成对输入事件的卷积操作,而且基于该卷积处理器所搭建的识别系统对MNIST数据库的识别效率可以达到90.57%。This paper presents a small size event-based convolution processor for feature extraction of the data generated by dynamic vision sensors（DVS）.It consists of a 32 pixel×32 pixel array,a RAM array that stores the convolution kernel,a left/right shift block,a control block,and an asynchronous event readout block.In order to reduce the area of convolution chip,a kernel RAM of 32×32 2 bit word is implemented to store the kernels.In each pixel unit,a 7bit counter is used to accomplish the accumulation instead of a traditional accumulator for smaller pixel size.In the 0.18 μm CMOS technology,each convolution unit occupies 37.5 μm×40 μm.The minimum latency between input and output event flows can be nearly 17 ns.Input event throughput can reach 12.5 Meps.Furthermore,a categorization system is established based on this convolution module,which consists of 16 assembled convolution modules for feature extraction and a spiking neural networks（SNN）for recognition.The experimental results show that the proposed convolution processor can achieve ideal convolution results.With the recognition system,the experimental results of MNIST show that the convolution module configured with 2 bit kernel weights resolution can also complete the feature extraction which achieves a recognition rate of 90.57%.

关 键 词：动态视觉传感器 地址事件表示 小尺寸芯片 卷积芯片 MNIST 脉冲神经网络 

分 类 号：TN47[电子电信—微电子学与固体电子学]