超深亚微米数字集成电路版图验证技术  

Layout Verification Technologies for SDSM Digital ICs

作　　者：吕江萍 陈超 胡巧云 

机构地区：[1]中国兵器工业第214研究所,江苏苏州215163

出　　处：《电子与封装》2017年第8期16-20,共5页Electronics & Packaging

摘　　要：在超深亚微米工艺中,数字集成电路版图设计由以前简单的物理验证进入到复杂的版图验证阶段。版图验证包含时序验证、形式验证和物理验证。时序验证进行电压降分析和时序分析,确保时序收敛;形式验证进行两个网表的逻辑等效检查;物理验证进行可制造性、可靠性和设计规则检查,确保版图符合可制造性工艺规则和电路规则。三种验证技术共同指导并约束着数字集成电路的物理实现,灵活配置相关版图验证技术可进一步加快版图验证的进度。The layout design technology in SDSM digital ICs has evolved from simple physical verification to complicated layout verification. Layout verification consists of timing verification, formal verification and physical verification. The timing verification performs IR Drop analysis and timing analysis and ensures clock convergence. The formality verification performs equivalence checking of two net-lists. The physical verification performs DFM, reliability and design rule check and ensures that the layout complies with DFM rule and electric circuit rule. The verification technologies jointly guide and control the physical realization of digital ICs. Flexibly selection and collocation of layout verification technologies improve layout verification efficiency.

关 键 词：超深亚微米 版图验证 时序验证 形式验证 

分 类 号：TN402[电子电信—微电子学与固体电子学]