基于倒装芯片焊球阵列封装的高速串行器/解串器接口的信号完整性分析与优化  

Signal integrity Analysis and Optimization Study of High-Speed Ser Des interface on Flip-Chip Ball Grid Array Package

作　　者：任晓黎 孙拓北 庞建 张江涛 

机构地区：[1]深圳市中兴微电子技术有限公司

出　　处：《中国集成电路》2017年第9期66-70,74,共6页China lntegrated Circuit

基　　金：国家自然科学基金(00000000);国家高技术研究发展计划(863计划)(2008AA000000)

摘　　要：串行器/解串器接口是一种高速率的串行数字接口。高度定制化的串行器/解串器接口的通道数据速率可达到28吉比特每秒或更高。在本文中,研究了用于高速网络数据传输应用的28吉比特每秒串行器/解串器接口倒装芯片封装设计对信号传输质量的影响。使用Cadence的3D-EM电磁场仿真工具来实现多层倒装芯片封装基板的信号完整性分析与设计优化,以获得最佳的插入和回波损耗。另外,本文还研究了在芯片封装级别影响串行器/解串器接口信号传输性能的因素以及控制信号传输质量的方法。The serializer/deserializer（Ser Des） interface is a high-speed serial digital interface. The highly customizable serializer/deserializer interface has a channel data rate of up to 28Gb/s or higher. In this paper, the effects of28Gb/s serializer/deserializer flip chip package design on signal transmission quality for high speed network data transmission applications have been studied. Cadence＇s 3DEM electromagnetic field simulation tool was used for signal integrity analysis and design optimization of the multi-layer flip-chip ball grid array（FCBGA）substrates. In addition, this paper also studied the factors that affect the signal transmission performance of the serializer/deserializer interface and the methods of controlling the transmission quality of the signal at the package level.

关 键 词：串行器/解串器 倒装芯片封装 信号完整性 CADENCE 3D-EM 

分 类 号：TN405[电子电信—微电子学与固体电子学]