一种新型低功耗抗软错误锁存器  

A Novel Low Power Consumption Soft Error-tolerant Latch

作　　者：张章[1] 周宇澄[1] 刘俊丞 程心[1] 解光军[1] 

机构地区：[1]合肥工业大学电子科学应用物理学院,合肥230009

出　　处：《电子与信息学报》2017年第10期2520-2525,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61404043;61674049;61401137)~~

摘　　要：该文提出一种新型的C单元的连接方法,将距离输出节点比较远的P型和N型晶体管的栅端与C单元的输出节点相连接,利用晶体管自身的反馈机制形成反馈路径,实现了自恢复功能,因此大幅降低动态消耗和硬件开销;采用点加强型C单元作为输出级电路并进行优化,使得电路抵御单粒子翻转的能力更强;基于上述改进,搭建出一个新的抗软错误锁存器,将输入信号经过传输门以后接传到输出端,以降低输入信号传到输出节点的延迟,利用节点之间的反馈比较机制进一步提升各个电路节点的临界电荷量。在22 nm的先进工艺下进行仿真,实验结果表明,提出的新型锁存器电路不仅具有优秀的抗软错误能力,并且在功耗延迟积方面比现有的锁存器电路性能提升了26.74%~97.50%。A novel C-element connect method is proposed. The gate of P-type/N-type transistor is modified trom the top/bottom of conventional C-element to connect to output, which takes advantage of the transistor＇s own feedback mechanism to form a feedback path to achieve the self-recovery function. Therefore; the dynamic performance and hardware overhead are significant reduced. The node-enhanced C-element is used as the output stage circuit and optimized, making the circuit more resistant to single event upset. Based on the above description a novel soft error-tolerant latch is proposed. Due to the only transmission gate in the shortest route between input and output, the delay in signal transmission is reduced. The critical charge can be further enhanced by using feedback comparison mechanism. Compared with latches in literature at 22 nm CMOS process, the results show that the proposed latch performs greater in reliability and the power delay products improvement of proposed latch achieves 26.74%-97.50%.

关 键 词：锁存器 软错误 C单元 自恢复 

分 类 号：TN47[电子电信—微电子学与固体电子学]