一种实现时序快速有效收敛的时钟树综合方案  

A Clock Tree Synthesis Scheme for Fast and Effective Closure of Timing

作　　者：刘慧君 谢亮 金湘亮 LIU Huijun XIE Liang JIN Xiangliang(School of Physics and Optoelectronics, Xiangtan University, Xiangtan, Hunan 411105, P. R. China Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on a Chip, Xiangtan, Hunan 411105, P. R. China)

机构地区：[1]湘潭大学物理与光电工程学院,湖南湘潭411105 [2]微光电与系统集成湖南省工程实验室,湖南湘潭411105

出　　处：《微电子学》2017年第5期670-673,共4页Microelectronics

基　　金：国家自然科学基金资助项目(61233010);湖南省自然科学杰出青年基金资助项目(2015JJ1014)

摘　　要：针对低频下数字集成电路实现时序收敛需要插入大量缓冲器而导致芯片布线困难、运行时间较长等问题,提出了一种降低时钟树级数与增加保持时间余量相结合的时钟树综合方案。基于CSMC 0.35μm CMOS工艺,采用提出的方案,使用IC Compiler和Prime Time工具,分别完成了应用于高精度隔离型Σ-ΔADC芯片的低速数字滤波器的物理设计以及静态时序分析。结果表明,与传统方案相比,保持时间负松弛总值降低了95.62%,时序收敛所需缓冲器个数减少了约98.13%,运行时间缩短了97.25%,有效地降低了布线拥塞程度,快速有效地实现了时序收敛。In the case of low frequency,mass buffers need to be inserted to achieve the timing closure of digital integrated circuit,which causes many problems such as wiring difficulty of chip,long time of running.A clock tree synthesis scheme of combining the decrease of clock tree series and the increase of hold time margin was proposed.Based on CSMC 0.35μm process,adopting the proposed scheme,the physical design and static timing analysis applied to low speed digital filters in high precision isolated Σ-Δ ADC chips were completed respectively by IC Compiler and Prime Time tools.The results showed that,compared with that of the traditional scheme,the hold time total negative slack was reduced by 95.62%.The number of required buffers for timing closure was reduced by about 98.13%.The running time was shortened by 97.25%.The wiring congestion level was effectively reduced.The timing closure was achieved quickly and effectively when the proposed scheme was used.

关 键 词：时钟树综合 静态时序分析 时序收敛 

分 类 号：TN402[电子电信—微电子学与固体电子学]