一种容SEU的新型自恢复锁存器  

A New SEU Tolerant Self-Recovery Latch

作　　者：黄正峰[1] 付俊超 欧阳一鸣[2] 闫爱斌 梁华国[1] 易茂祥[1] HUANG Zhengfeng FU Junchao OUYANG Yiming YAN Aibin LIANG Huaguo YI Maoxiang(School of Electronic Science ＆ Applied Physics, Hefei University of Technology, Hefei 230009, P. R. China School of Computer and Information, Hefei University of Technology, Hefei 230009, P. R. China School of Computer Science and Technology, Anhui University, Hefei 230601, P. R. China)

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009 [2]合肥工业大学计算机与信息学院,合肥230009 [3]安徽大学计算机科学与技术学院,合肥230601

出　　处：《微电子学》2017年第5期685-689,694,共6页Microelectronics

基　　金：国家自然科学基金资助项目(61574052;61674048;61604001;61474036;61371025);安徽省自然科学基金资助项目(1608085MF149)

摘　　要：针对单粒子翻转(SEU)的问题,提出了一种容SEU的新型自恢复锁存器。采用1P-2N单元、输入分离的钟控反相器以及C单元,使得锁存器对SEU能够实现自恢复,可用于时钟门控电路。采用高速通路设计和钟控设计,以减小延迟和降低功耗。相比于HLR-CG1,HLR-CG2,TMR,HiPer-CG锁存器,该锁存器的功耗平均下降了44.40%,延迟平均下降了81%,功耗延迟积(PDP)平均下降了94.20%,面积开销平均减少了1.80%。A new latch was proposed to deal with the single event upset.The 1 P-2 Nunit,the clock-controlled inverters with separated inputs and the C unit were adopted,so the proposed latch could self-recover when particles striked on any one of its single node.Furthermore,it could be used for the clock gating circuits.Fast paths and clock-controlled circuits were applied to reduce the delay and power consumption.Compared to that of HLR-CG1,HLR-CG2,TMR and HiPer-CG hardening latches,the power consumption of the proposed latch had been reduced by 44.40%,the delay by 81%,the power delay product by 94.20%,and the area cost by 1.80%.

关 键 词：软错误 单粒子翻转 时钟门控 加固锁存器 

分 类 号：TN79[电子电信—电路与系统] TN406