一种缓冲器阻抗动态调整的LDO  

An LDO with Buffer Impedance Dynamic Adjustment

作　　者：胡云斌[1,2] 胡永贵[3] 周前能[1,3] 

机构地区：[1]重庆邮电大学,重庆400065 [2]模拟集成电路重点实验室,重庆400060 [3]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2017年第6期739-742,共4页Microelectronics

基　　金：模拟集成电路重点实验室基金资助项目(9140C090113150C09043)

摘　　要：提出了一种缓冲器阻抗动态调整的LDO结构。采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响。该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能。基于TSMC 0.18μm 3.3VCMOS工艺进行设计,该LDO的输出电压为1.8V,压差电压为0.2V,最大输出电流为100mA。仿真结果显示,LDO的静态电流只有5μA,当负载电流在10ns内从0mA跳变到100mA时,输出欠冲和过冲电压分别为88.2mV和34.8mV。A low-dropout regulator（LDO）with an impedance dynamic adjustment buffer was presented.Shunt negative feedback and impedance dynamic adjustment technology were used in the buffer to low the output impedance without increasing the extra quiescent current.Therefore,the pole at the gate of the power device was far beyond the unit gain frequency（UGF）and had almost no effect on the stability.In addition,the proposed buffer could significantly increase the slew rate at the gate of the pass device,thus having improved the transient performance of the LDO.Based on TSMC 0.18μm 3.3 VCMOS process,an LDO with 1.8 V output voltage,0.2 V dropout voltage and 100 mA maximum load current was designed.Simulation results showed that the LDO＇s quiescent current was only 5μA.The maximum overshoot and undershoot were 88.2 mV and 34.8 mV respectively with a load step change of 100 mA/10 ns.

关 键 词：低压差线性稳压器 源级跟随器 快速瞬态响应 

分 类 号：TN432[电子电信—微电子学与固体电子学]