RV32I控制单元设计与实现  

Design and Implementation of Control Element of RV32I

作　　者：张迅珍 梁青 李涛 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《微电子学与计算机》2018年第3期74-78,82,共6页Microelectronics & Computer

摘　　要：针对新型开源精简指令集架构RISC-V指令集,设计了一款支持32位基本指令集的处理器(RV32I),其外围电路包含快速存储(QMEM)、高速缓存(Cache)和双倍速率同步动态随机存储器(DDR)等存储设备,主要描述其控制单元的设计与实现.设计采用经典三级流水线,即取指、译码和执行,通过有限状态机支持流水线,并且使用可综合的Verilog HDL语言描述,预留中断异常控制模块.仿真结果表明,该控制单元能够实现流水线正常稳定的运转.RV32I, a processor that supports 32-bit basic instruction sets,is designed to support the new open Reduced Instruction Set Computer RISC-V instruction set. The memory devices of its peripheral circuits include Quick Memory, （;ache Memory and Synchronous Dynamic Random Access Memory. This paper focuses on the design and implementation of the control element of RV32I. It uses the classic three-stage pipeline-via finite-state machine to support-fetch, decode and execute and uses the synthesizable Verilog HDL language to describe. And reserved the control element of interrupt and exception. Simulation results show that the control element can realize the the pipeline operation normal and stable.

关 键 词：RISC-V CACHE DDR 三级流水线 有限状态机 VERILOG HDL 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]