一种宽频带CMOS高速锁相环  

A Broadband CMOS High Speed Phase Locked Loop

作　　者：王兰[1] 胡刚毅[2] 张瑞涛[2] 胡云斌[1] 

机构地区：[1]重庆邮电大学光电工程学院,重庆400065 [2]模拟集成电路重点实验室,重庆400060

出　　处：《微电子学》2018年第1期1-4,共4页Microelectronics

基　　金：模拟集成电路重点实验室基金资助项目(0C09YJTJ1602)

摘　　要：基于55nm CMOS工艺,设计了一种宽频带高速锁相环(PLL)。PLL中的压控振荡器(VCO)采用8位开关电容阵列和变容管阵列,实现了对VCO振荡频率的调节和不同频段之间的切换。VCO采用分段式结构,实现了8.7~12.5GHz的宽频率范围。分段结构中,每个频段的频率增益K_(vco)较低,实现了良好的相位噪声性能。仿真结果表明,在1.2V电源电压下,该PLL的最高工作频率为12.5GHz,锁定时间为小于2.5μs,相位噪声为-106dBc·Hz^(-1)@1 MHz。A high speed phase locked loop（PLL）circuit with a wide bandwidth was designed in a 55 nm CMOS technology.The voltage-controlled oscillator consisted of an 8 bit switched capacitor array and a varactor array,which was applied to regulate the VCO oscillation frequency and to switch the bands with different frequencies.A segmented structure was used in the VCO to reach a broadband coverage from 8.7 to 12.5 GHz.Because the frequency gain（K（vco））of each frequency band was low in the segmented structure,a nice performance of phase noise was obtained.The simulation results showed that the maximum working frequency of the PLL was 12.5 GHz at a 1.2 Vsupply,the lock time was less than 2.5μs,and the phase noise was -106 dBc·Hz^-1 at a 1 MHz offset from 12.5 GHz.

关 键 词：锁相环 压控振荡器 开关电容阵列 变容管阵列 

分 类 号：TN911.8[电子电信—通信与信息系统] TN752[电子电信—信息与通信工程]