级联式伺服脉冲发生器设计  

Design of the Cascading Servo Pulse Generator

作　　者：王宝仁[1] 韩文强[1] WANG Bao-ren;HAN Wen-qiang(College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590, Chin)

机构地区：[1]山东科技大学机械电子工程学院

出　　处：《控制工程》2018年第4期549-553,共5页Control Engineering of China

摘　　要：针对传统控制系统扩展性弱和目前网络化控制系统复杂的现状，提出了一种级联式多轴伺服运动控制方案，采用SPI总线作为通信媒介，通过级联实现多伺服轴的网络化连接。对级联系统结构、工作原理进行了详细的论述，对通信报文结构进行了设计规划。基于FPGA硬件平台，采用VerilogHDL硬件描述语言，完成了级联式脉冲发生器的设计，用ModeISim进行时序测试仿真，然后通过硬件实验验证了该方案的有效性。通过该级联式伺服脉冲发生器，普通伺服驱动器和步进电机驱动器可以很方便的实现网络化连接，尤其适应于多电机、远距离分布的运动控制系统。Aiming at the weak extensibility of the traditional control system and the complex state of the networked control system, a scheme of cascading multi-axial servo motion control is presented. By adopting SPI bus as the communication medium, the networked connection of multi-servo axis is realized via cascading. The structure and working principles of the cascaded system are described in detail and then the structure of the communication message is planned. Based on FPGA hardware platform, the cascaded pulse generator is designed by adopting Vefilog HDL. By using ModelSim for simulation of timing sequence test, this scheme is verified feasible via hardware experiments. The common servo driver and stepper motor driver can be easily connected with network by using this cascaded servo pulse generator, which is especially suitable for the motion control system featuring multi-motor and remote distributing.

关 键 词：脉冲发生器 级联 SPI FPGA VERILOG HDL 

分 类 号：TP23[自动化与计算机技术—检测技术与自动化装置]