一种低抖动快锁定的时钟数据恢复电路设计  

Design of a low jitter and fast locking clock and date recovery circuit

作　　者：胡腾飞[1] 方毅[2] 黄鲁[1] Hu Tengfei;Fang Yi;Huang Lul(Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, Chin;Information Science Center, University of Science and Technology of China, Hefei 230027, China)

机构地区：[1]中国科学技术大学电子科学与技术系,安徽合肥230027 [2]中国科学技术大学信息科学技术实验中心,安徽合肥230027

出　　处：《信息技术与网络安全》2018年第3期113-116,121,共5页Information Technology and Network Security

摘　　要：采用TSMC 0.13μm CMOS工艺,设计了一种基于延迟锁相环(DLL)与锁相环(PLL)混合技术的时钟数据恢复(CDR)电路。它结合延迟锁相环电路追踪速度快和锁相环电路抖动抑制能力强的特点,与通常基于二阶锁相环结构的电路相比,在输出抖动相同的情况下,具有更快的锁定时间。仿真结果表明该电路可以成功恢复出480 MHz伪随机数据,数据峰峰值抖动约为39 ps,即相对抖动约为0.02 UI,锁定时间约为793 ns,较二阶锁相环结构的电路提升了32%。芯片核心电路面积为0.15 mm2,1.2 V电源供电下消耗功耗6.9 m W。A clock and date recovery circuit（CDR） which consists of delay locked loop（DLL） and phase locked loop（PLL） is designed in TSMC 0. 13 μm CMOS technology. Compared to a standard second-order loop,it provides a lower jitter through combining fast acquisition of DLL and strong jitter suppression of PLL. The simulation results show that with 480 MHz pseudo-random-binary-sequence（PRBS） input,the recovered date has a peak-to-peak jitter of 37 ps,namely a relative jitter of 0. 02 UI. The whole chip occupies a core area of 0. 15 mm2 and dissipates 6. 9 m W under 1. 2 V supply voltage.

关 键 词：锁相环 延迟锁相换 时钟数据恢复 

分 类 号：TN43[电子电信—微电子学与固体电子学]