基于FPGA的卷积神经网络的实现  

The Realization of the Convolution Neural Network Based on FPGA

作　　者：李嘉辉 蔡述庭[1] 陈学松[1] 熊晓明[1] Li Jiahui;Cai Shuting;Chen Xuesong;Xiong Xiaoming(School of Automation, Guangdong University of Technolog)

机构地区：[1]广东工业大学自动化学院

出　　处：《自动化与信息工程》2018年第1期32-37,共6页Automation & Information Engineering

基　　金：国家自然科学基金(61201392);广东省自然科学基金-自由申请项目(2015A030313497)

摘　　要：现有基于CPU或GPU的卷积神经网络实现方案,无法兼顾实时性、功耗以及便携性的要求。基于FPGA强大的并行处理能力和超低功耗,在DE1-Soc开发板上采用Verilog HDL实现了使用MNIST数据集的阿拉伯数字手写体识别卷积神经网络。网络的每一层采用流水线和时分复用方法;单个时钟周期能完成72次乘累加操作,在100 MHz的工作频率下,加速器峰值运算速度可达7.2 GMAC/s。与PC上运行的定点数版本的C语言程序相比,在相同错误率6.43%的情况下,速度是其5.2倍。Convolutional Neural Network is a computation intensive algorithm based on deep learning,and it is common used in image classification,video recognition,etc.Due to the powerful parallel capability and flexibility of FPGA,it is frequently used as the platform to implementation of CNN.Meanwhile,the rapidly emerging mobile application of deep learning suggest that it is very significant to implement a CNN on mobile platform.Therefore,a DE1-Soc development board was used to implement a CNN network by Verilog HDL approach,using mnist as samples data.Finally,the implementation is 5.2 times faster than that on PC.

关 键 词：卷积神经网络 FPGA 性能加速 

分 类 号：TN791[电子电信—电路与系统] TP183[自动化与计算机技术—控制理论与控制工程]