系统级封装的片上和板级协同ESD保护方案  

An ESD Protection Strategy with Chip-Level and Board-Level Co-Design Applied in SiP

作　　者：黄晓宗[1,2] 干旭春[2] 刘凡 刘志伟[1] 黄文刚 朱冬梅[2] 王国强[2] 成辉[1] HUANG Xiaozong;GAN Xuchun;LIU Fan;LIU Zhiwei;HUANG Wengang;ZHU Dongmei;WANG Guoqiang;CHENG Hui(School of Microelec. and Solid-State Elec. , Univ. of Elec. Sci. and Technol. of China, Chengdu 610054, P. R. China;Sichuan Institute of Solid-State Circuits, China Elec. Technol. Group Corp. , Chongqing 400060, P. R. China)

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2018年第2期141-145,共5页Microelectronics

摘　　要：提出了一种面向系统级封装(SiP)的片上和板级协同设计方案,提升了电路的ESD性能。该SiP系统集成了若干驱动放大器、ADC和电阻电容。虽然集成的芯片引脚均可满足2 000V的HBM ESD能力,但因为封装尺寸为0402的高精度薄膜电阻会受到损伤,所以SiP仅能承受600V的ESD冲击。在SiP中增加了高速开关二极管1N4148,以泄放ESD冲击电流,使得该SiP集成电路系统的ESD能力从600V提升至2 500V。片上与板级协同设计方法能显著提升产品的可靠性,可广泛应用于SiP产品中。The co-design ESD protection strategy for system in package（SiP）with on-chip and on-board components was discussed and analyzed to enhance the ESD robustness of the modules.A mixed-signal converting system with several driving amplifiers and an ADC converter failed under human body model stresses of 600 Vdue to the ESD sensitivity of the input thin film resistors with the size of 0402,even though every die survived under the HBM stress of 2 000 Vat all pins.The high speed switching diodes 1 N4148 were integrated on the SiP’s substrate to shunt the ESD current,so the ESD robustness of SiP was improved from 600 V to 2 500 V.This solution provided guidelines for the co-design of SiP ESD protection to improve the reliability.

关 键 词：ESD保护 片上和板级协同设计 寄生效应 系统级封装 

分 类 号：TN402[电子电信—微电子学与固体电子学]