SVM的并行计算结构研究及FPGA实现  

Research on Parallel Computing Architecture of SVM and Implementation on FPGA

作　　者：胡福平 徐美华[2] 沈华明 HU Fu-ping;XU Mei-hua;SHEN Hua-ming(Microelectronic R＆D Center, Shanghai University, Shanghai 200072, China;, School of Mechatronie Engineering Automation Shanghai University, Shanghai 200072,China)

机构地区：[1]上海大学微电子研究与开发中心,上海200072 [2]上海大学机电工程与自动化学院,上海200072

出　　处：《微电子学与计算机》2018年第6期79-83,共5页Microelectronics & Computer

基　　金：国家自然科学基金(61376028;61674100)

摘　　要：本文基于FPGA平台提出了一种用于SVM硬件实现的并行计算结构,利用Verilog HDL语言完成了各模块的结构设计,并进行了仿真和实验验证.仿真结果表明对比Libsvm的训练时间,该并行结构实现了3.5倍的加速比.实验结果表明在相同的参数条件下,该结构实现的SVM的分类性能要略优于Libsvm,分类效果得到了保证,并且最大时钟频率能达到190.331 MHz,具有较高的计算效率.Based on the FPGA platform,aparallel computing structure for SVM hardware implementation is proposed.The structure design of each module is accomplished by using Verilog HDL language,then simulation and experimental verification are carried out.Simulation results show that compared with Libsvm training time,the parallel architecture achieves a speed-up ratio of 3.5 times.The experimental results show that with the same parameters,the classification performance of this structure is superior to the Libsvm slightly,the classification effect is guaranteed,and the maximum clock frequency can reach 190.331 MHz,it has high computational efficiency.

关 键 词：支持向量机 FPGA 模式分类 并行计算结构 

分 类 号：TN47[电子电信—微电子学与固体电子学]