提高SoC系统级仿真效率的研究  

Research on Improve SoC System Level Verification Efficiency

作　　者：张修钦 罗军 郭涛 王成伟 ZHANG Xiuqin;LUO Jun;GUO Tao;WANG Chengwei(Xi＇an UnilC Semiconductors Co. Ltd, Shaanxi 710075, China.)

机构地区：[1]西安紫光国芯半导体有限公司,陕西710075

出　　处：《集成电路应用》2018年第6期15-17,共3页Application of IC

基　　金：国家科技重大专项"核高基"国家高技术发展计划课题项目

摘　　要：分析了业界常用的SoC(System on Chip)系统级验证方法,并阐述了提高SoC系统级仿真效率的三种方法。一是通过VIP(Verification Intellectual Property)代替CPU(Central Processing Unit)来加速仿真,二是通过空逻辑来代替相关模块实际代码来加速仿真,三是通过仿真工具(VCS)自带的功能来加速仿真。This paper analyzes the SoC（System on Chip） system-level verification method commonly used in the industry, and introduce three methods to improve the SoC systemlevel simulation efficiency. One is to speed up the simulation by replacing the CPU（Central Processing Unit） with the VIP（Verification Intellectual Property）, the second is to accelerate the simulation by replacing the actual code of the relevant module with the empty logic, and the third is to accelerate the simulation through the function of the simulation tool（VCS）.

关 键 词：集成电路设计 SOC验证 仿真加速 VCS 

分 类 号：TN402[电子电信—微电子学与固体电子学]