LV/HV P-Well BCD[B]技术(1)的芯片与制程剖面结构  

Structure of LV/HV P-Well BCD[B] Chip(1) and Process

作　　者：潘桂忠 PAN Gu zhong(Shanghai Belling Co., Ltd, Shanghai 200233, China;The 771 Electronics Technique Institute of China Aerospace Science and Technology Research Academy, Shaanxi 710600, China.)

机构地区：[1]上海贝岭股份有限公司,上海200233 [2]中国航天电子技术研究院第七七一研究所,陕西710600

出　　处：《集成电路应用》2018年第6期41-45,共5页Application of IC

基　　金：上海市软件和集成电路产业发展专项基金(2009.090027)

摘　　要：LV/HV P-Well BCD[B]技术(1)能够实现低压5 V与高压100～700 V(或更高)兼容的BCD工艺。为了便于高低压MOS器件兼容集成,采用源区为硼磷双扩散形成沟道的具有漂移区的偏置栅结构的HV LDMOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到不同的高电压。采用MOS集成电路芯片结构设计﹑工艺与制造技术,依该技术得到了芯片制程结构。LV/HV P-Well BCD[B] Technology（1） can realize BCD technology compatible with low voltage 5 V and high voltage 100～700 V（or higher）. In order to facilitate compatible integration of high and low voltage MOS devices, a HV LDMOS device with drift region of the bias gate structure is used to form a channel with boron, phosphorus and double diffusion in the source region. The high voltage can be obtained by changing the length, width, junction depth and doping concentration of the drift region. The MOS integrated circuit chip structure design, process and manufacturing technology are adopted, and the chip process structure is obtained based on this technology.

关 键 词：集成电路制造 HV LDMOS结构 LV/HV P-WELL BCD[B]芯片结构 制程剖面结构 

分 类 号：TN405[电子电信—微电子学与固体电子学]