高速超大规模集成电路的陶瓷基板设计  

Design of Ceramic Substrate for High Speed VLSI

作　　者：敖国军 张国华 杨兵[1] AO Guo-jun;ZHANG Guo-hua;YANG Bing(No.58 Research Institute of CETC,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第58所,江苏无锡214035

出　　处：《混合微电子技术》2018年第1期51-57,共7页Hybrid Microelectronics Technology

摘　　要：随着集成电路向着高密度、高速方向发展，保证高速信号的可靠传输成为封装基板电学设计中的重要组成部分。本文完成了一款工作频率达到8GHz的高速超大规模集成电路的陶瓷基板设计，首先从频域角度来对基板电学性能进行评估，采用ansys公司HFSS软件对关键差分信号进行仿真，在8GHz以内插入损耗始终大于-0．6dB，回波损耗小于-20dB。其次从时域角度来对基板电学性能进行进一步评估，采用ansys公司的designer软件对关键差分信号进行仿真，进行芯片、封装、PCB板协同仿真，得到眼图的最小眼高为565mV，最小眼宽为147．2ps，满足了高速超大规模集成电路的设计要求。As integrated circuits move toward high density and high frequency, ensuring reliable transmission of high speed signals becomes an important part of the electrical design of packaging substrates. This paper describes the design of ceramic substrate with the frequency of 8GHz for high speed VLSI. Firstly the substrate electronic design is assessed in frequency - domain, the insertion loss of critical differential signal can keep above -0.6dB, and the return loss can keep below -20dB in the frequency of 8GHz by the HFSS simula- tion software of Ansys. Secondly, co - simulation method of die, package and PCB further assess the substrate elec- tronic design in time -domain by the designer simulation software of Ansys, the minimum eye height is 565mv, the minimum eye width is the 147.2ps,it meets the design requirements of high soeed VLSI.

关 键 词：高速超大规模集成电路 陶瓷基板 传输特性 插入损耗 回波损耗 

分 类 号：TM283[一般工业技术—材料科学与工程]