面向互连的综合策略  

A Wire-Centered Synthesis Policy

作　　者：马光胜[1] 杜振军[1] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,哈尔滨150001

出　　处：《计算机工程与应用》2002年第20期27-29,共3页Computer Engineering and Applications

基　　金：国家自然科学基金项目资助(编号:69973014)

摘　　要：VDSM(超深亚微米)设计中互连线延迟已在电路延迟中起到决定性作用。在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题,尚未有成熟的方法。文章提出了一种面向互连延迟的综合策略,将前期设计定时规划,前期设计的线网规划和布局规划方法相融合,并在不同阶段给出了不同精度和复杂度的定时分析模型。文中还给出了一个设计实例对该文的综合策略予以了说明。Interconnect delay is becoming a deterministic factor in VDSM design.Considering interconnect delay in early design stages is a hot spot and how to establish an interconnect-centered synthesis method is a hard task,yet without mature approaches.In this paper,a wire-centered synthesis policy is presented,in which timing planning,wire planning and IP based floorplanning in early designs are considered, also several Boolean Process based delay analysis methods are adopted.A design example is given to show the approach in this paper.

关 键 词：综合策略 超深亚微米 Boole过程论 互连延迟 模拟电路 设计 

分 类 号：TN710[电子电信—电路与系统]