薄栅介质陷阱密度的求解和相关参数的提取  

Solving Process of Trap Density and Extracting of Correlative Parameters in Thin Gate Dielectric

作　　者：刘红侠[1] 郝跃[1] 

机构地区：[1]西安电子科技大学微电子研究所,西安710071

出　　处：《Journal of Semiconductors》2002年第9期952-956,共5页半导体学报（英文版）

基　　金：国家高技术研究与发展计划资助项目 (No.863 -So C-Y-3 -6-1)~~

摘　　要：采用恒定电流应力对薄栅氧化层 MOS电容进行了 TDDB评价实验 ,提出了精确测量和表征陷阱密度及累积失效率的方法 .该方法根据电荷陷落的动态平衡方程 ,测量恒流应力下 MOS电容的栅电压变化曲线和应力前后的高频 C- V曲线变化求解陷阱密度 .从实验中可以直接提取表征陷阱的动态参数 .在此基础上 ,可以对器件的累积失效率进行精确的评估 .TDDB evaluation experiments are implemented on the thin gate oxides MOS capacitor,and a method of precise measurement and characterization the trap density and accumulative failure are presented.Based on dynamic equilibrium equation in the process of trapped charges,the method can obtain the trap density by measuring the change of gate voltage of MOS capacitance under constant current stress and the change of high frequency C V curve before and after the stress.The dynamitic parameters of characterization the trap density can be extracted from the experiment.On the base of experiment,the accumulation failure of devices can be evaluated precisely.

关 键 词：薄栅氧化膜 经时击穿 陷阱密度 累积失效率 CMOS集成电路 

分 类 号：TN406[电子电信—微电子学与固体电子学]