系统芯片I_(DDQ)可测试设计规则和方法  

The Methods and Rules of Design for I_(DDQ) Testing of System on Chip

作　　者：冯建华[1] 孙义和[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《测试技术学报》2002年第3期162-166,共5页Journal of Test and Measurement Technology

摘　　要：目的　为了使 IDDQ测试方法对 SOC(系统芯片 ) IC能继续适用 ,必须实现 SOC IDDQ的可测试性设计 ,解决因 SOC设计的规模增大引起漏电升高问题 .方法　传统的电路分块测试方法存在需要增加引腿代价 ,因此是不实际的 .本文提出了一种通过 JTAG边界扫描控制各个内核电源的 SOC IDDQ可测试设计方法 .结果　实验表明该设计不要求专门的控制引腿 ,硬件代价是可忽略的 .结论　本文提出的方法可有效地用于系统芯片的Aim\ To make I\-\{DDQ\} testing to be available, it is necessary to implement design for I\-\{DDQ\} testing of System on a Chip(SOC)and to solve the issue of increased leakage due to enormous size of the SOC design. Methods\ Traditional circuit partitioning methods need to be added pin overhead, so it is not available. A method of design is presented for I\-\{DDQ\} testing of SOC that facilitates I\-\{DDQ\} testing by controlling power supply of the individual cores through JTAG boundary scan. Results\ The results show that the design does not require any dedicated pins to control the power down signals and the hardware overhead in this design is negligible. Conclusions\ The suggested method can be effectively used to the I\-\{DDQ\} testing of System on a Chip.

关 键 词：系统芯片 可测试性设计 内核 IDDQ测试 SOC 集成电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]