系统芯片中低功耗测试的几种方法  

Several Methods of Low Power Testing in System on a chip

作　　者：蒋敬旗[1] 周旭[1] 李文[1] 范东睿[1] 

机构地区：[1]中国科学院计算技术研究所,北京100080

出　　处：《微电子学与计算机》2002年第10期20-23,共4页Microelectronics & Computer

基　　金：国家863计划项目(2001AA111070)

摘　　要：在系统芯片可测试性设计中考虑功耗优化问题是当前国际上新出现的研究领域。在可测试性设计中考虑功耗的主要原因是数字电路在测试方式下的功耗比系统在正常工作方式下高很多。测试期间的功耗会引发系统成本上升,可靠性降低,成品率下降。本文介绍低功耗测试技术中的一些基本概念,对已有的几种主要的降低测试功耗方法进行分析,最后给出一种高性能微处理器的真速低功耗自测试方法。Considering power optimization in design for testability of system-on-a-chip is a newly emerging research region. Its main reason is that the power assumption of digital circuits in test mode is very higher than that in normal system operation mode. Power during testing can make system cost high, reliability low,yield down. In this paper, some basic concepts of low power testing techniques are introduced. Some main existing methods of reducing testing power are analyzed. At the last,the development trends and some problems needed to resolve are pointed out.

关 键 词：系统芯片 低功耗 集成电路测试 可测试性设计 

分 类 号：TN407[电子电信—微电子学与固体电子学]