卫星导航抗干扰A/D芯片的可测试性设计  

Design for Testability of Satellite Navigation Anti-jamming A/D Chip

作　　者：舒钰[1] SHU Yu

机构地区：[1]中国电子科技集团公司第二十研究所,西安710068

出　　处：《现代导航》2017年第3期210-213,共4页Modern Navigation

摘　　要：ASIC集成电路设计开发中的瑕疵与电路故障是芯片实现的最大困难,本文详细介绍了基于130nm工艺的卫星导航抗干扰A/D芯片的可测性设计,并从测试的覆盖率、成本等方面提出了优化改进方案,该方案的测试覆盖率最高可达99.93%,并缩减了测试时间和成本,该芯片顺利通过量产,证明了可测试性设计的有效性。The flaw and circuit fault are most difficult situation in implementation of ASIC.In this paper,the design fortestability of satellite navigation anti-jamming A/D chip based on130nm process is introduced in detail,and the optimization andimprovement scheme from the coverage and cost of the test are put forward.The coverage of the scheme can reach99.93%,and thisdesign can reduce the test time and cost.This chip successfully through the mass production,proved the effectiveness of testabilitydesign.

关 键 词：可测试性设计 故障覆盖率 扫描链 

分 类 号：TN965[电子电信—信号与信息处理]