An On-chip Interconnection QoS Verification Platform of Processor of Large Data for Architectural Modeling Analysis  

作　　者：Li Qinghua Qin Jilong Ding Xu Wang Endong Gong Weifeng 

机构地区：[1]DTmobile Inc.,Beijing100083,China [2]AMD Inc.,Beijing100081 [3]National High-performance Computing and Storage Key Laboratory of Inspur,Beijing100085,China

出　　处：《国际计算机前沿大会会议论文集》2015年第1期126-128,共3页International Conference of Pioneering Computer Scientists, Engineers and Educators（ICPCSEE）

摘　　要：This paper presents introduction for a QoS verification of on-chip interconnection based on the new progress of the industry, which combined with an AMD processor chip design for big data. Some verification experience in architectural modeling and simulation of on-chip interconnection is also introduced in this paper.

关 键 词：INTERCONNECT QOS Verification Modeling MULTIPROCESSOR Computer Architecture Big Data 

分 类 号：C5[社会学]