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This paper presents the design of a Coherence-Free Processor(CFP)that enables a scalable multiprocessor by eliminating cache coherence operations in both hardware and software.The CFP uses a coherence-free cache(CFC)t...
This research is funded by Princess Nourah bint Abdulrahman University Researchers Supporting Project number(PNURSP2022R 151);Princess Nourah bint Abdulrahman University,Riyadh,Saudi Arabia.
Suspicious mass traffic constantly evolves,making network behaviour tracing and structure more complex.Neural networks yield promising results by considering a sufficient number of processing elements with strong inte...
Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of te...
Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of com...
Project(2020JJ4032)supported by the Hunan Provincial Natural Science Foundation of China。
Maintaining temporal consistency of real-time data is important for cyber-physical systems.Most of the previous studies focus on uniprocessor systems.In this paper,the problem of temporal consistency maintenance on mu...
the National Natural Science Foundation of China under Grant Nos.61572112 and 61802052;the Applied Basic Research Programs of Science and Technology Department in Sichuan Province of China under Grant No.2019YJ0185.
Coordinated partitioning and resource sharing have attracted considerable research interest in the field of real-time multiprocessor systems.However,finding an optimal partition is widely known as NP-hard,even for ind...
Project supported by Sama Technical and Vocational Training College,Islamic Azad University,Shoushtar Branch,Shoushtar,Iran
Optimized task scheduling is one of the most important challenges to achieve high performance in multiprocessor environments such as parallel and distributed systems. Most introduced task-scheduling algorithms are bas...
This paper considers the scheduling problem observed in chip sorting operation of LED manufacturing, where each lot (job) with release time have four operations to be processed on a set of processing stages without pr...
This paper presents introduction for a QoS verification of on-chip interconnection based on the new progress of the industry, which combined with an AMD processor chip design for big data. Some verification experience...
This work was supported by the National Natural Science Foundation of China under Grant Nos.61379040,61272131,61202053,61222204,and 61221062;the Natural Science Foundation of Jiangsu Province of China under Grant No.SBK201240198;the Fundamen-tal Research Funds for the Central Universities of China under Grant No.WK0110000034;the Open Project of State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences(CAS)under Grant No.CARCH201407;the Strategic Priority Research Program of CAS under Grant No.XDA06010403.
On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection met...