一种BCD码数/模转换器的设计  

Design of BCD code digital-to-analog converter

作　　者：华猛 黄伟军[1,2] 刘传洋 吴晨辉[1,2] HUA Meng;HUANG Weijun;LIU Chuanyang;WU Chenhui(Suzhou University of Science&Technology,Suzhou 215009,China;Suzhou Intelligent Measurement&Control Engineering Technology Research Center,Suzhou 215009,China)

机构地区：[1]苏州科技大学,江苏苏州215009 [2]苏州市智能测控工程技术研究中心,江苏苏州215009

出　　处：《现代电子技术》2018年第16期26-30,共5页Modern Electronics Technique

基　　金：省建设厅系统科技项目(2014JH12);住房和城乡建设部科技项目(2014-K8-050)~~

摘　　要：提出一种8421BCD码输入的CMOS数/模转换器。数/模转换器输入采用8421BCD码并行数字码输入方式,输出采用模拟电压输出的方式,内部电阻网络根据8421BCD码特点进行特殊设计;锁存电路采用时钟控制,极大地抑制毛刺干扰。电路设计是基于0.35μm CMOS工艺,经HSpice软件和Cadence软件仿真表明,电路工作在3.3 V电压下,8421BCD码数/模转换器的积分非线性误差(INL)最大为-0.48 LSB和微分非线性误差(DNL)最大为-0.39 LSB,优值(FOM)最大为3.96,电路功耗为0.97 m W。A digital-to-analog converter of 8421BCD code input is proposed.For the digital-to-analog converter,the parallel digital code 8421BCD code is used as the input mode,analog voltage output is used as the output mode,and the internal resistance network is specially designed according to the characteristics of the 8421BCD code.Clock control is adopted for the latch circuit to greatly restrain glitch impulses.The circuit design is based on the 0.35μm CMOS process.The results of the HSpice and Cadence software simulation show that the circuit works at 3.3 V voltage,the maximum integral non.linear(INL)error and differential non.linear(DNL)error of the 8421BCD digital.to.analog converter are–0.48 LSB and–0.39 LSB,the maximum figure of merit(FOM)is 3.96,and the power consumption of the circuit is 0.97 mW.

关 键 词：8421BCD码 数/模转换器 CMOS 内部电阻网络 时钟控制 HSPICE 

分 类 号：TN366-34[电子电信—物理电子学] TP432[自动化与计算机技术]