一种静电保护电路的版图设计研究  

Study on Layout of an Electrostatic Protection Circuit

作　　者：张登军 ZHANG Dengjun(Zhuhai Boya Technology Co.,Ltd,Guangdong 519080,China)

机构地区：[1]珠海博雅科技有限公司,广东519080

出　　处：《集成电路应用》2018年第12期4-6,共3页Application of IC

基　　金：广东省科技计划项目(2017B090908003)

摘　　要：国内存储器芯片快速发展,芯片的制造工艺不断提升,国内逻辑主流工艺发展到28 nm工艺节点,非挥发性存储器NAND Flash发展到24 nm工艺节点。芯片被广泛应用到各种电子产品中,集成电路芯片的ESD失效占用很大比例。它的可靠性问题越来越被关注,静电保护电路的设计和优化显得尤为重要。提出一种有效的静电保护电路版图,节约芯片面积,从而实现对芯片管脚的静电保护。With the rapid development of memory chips in China,the manufacturing process of memory chips has been improved continuously.The mainstream logic technology in China has developed to 28 nm process nodes,and the non-volatile memory NAND Flash has developed to 24 nm process nodes.Chips are widely used in various electronic products,and the ESD failure of IC chips accounts for a large proportion.Its reliability has been paid more and more attention.The design and optimization of the electrostatic protection circuit is particularly important.In this paper,an effective electrostatic protection circuit layout is proposed to save chip area and realize the electrostatic protection of chip pins.

关 键 词：集成电路设计 静电保护 版图设计 寄生三极管 静电泄放 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN432