基于FPGA的多通道FIFO存储控制器的设计与实现  

Design and implementation of multi-channel FIFO memory controller based on FPGA

作　　者：吕达 张加宏[1,2,3] 李敏[1,3] 冒晓莉[1,3] 杨天民 谢丽君 Lü Da;ZHANG Jiahong;LI Min;MAO Xiaoli;YANG Tianmin;XIE Lijun(School of Electronics and Information Engineering,Nanjing University of Information Science&Technology,Nanjing 210044,China;Jiangsu Collaborative Innovation Center of Atmospheric Environment and Equipment Technology,Nanjing University of Information Science&Technology,Nanjing 210044,China;Jiangsu Key Laboratory of Meteorological Observation and Information Processing,Nanjing University of Information Science&Technology,Nanjing 210044,China)

机构地区：[1]南京信息工程大学电子与信息工程学院,江苏南京210044 [2]南京信息工程大学江苏省大气环境与装备技术协同创新中心,江苏南京210044 [3]南京信息工程大学江苏省气象探测与信息处理重点实验室,江苏南京210044

出　　处：《现代电子技术》2019年第4期1-4,9,共5页Modern Electronics Technique

基　　金：国家自然科学基金项目(61306138);国家自然科学基金项目(41605120);江苏省气象探测与信息处理重点实验室/江苏省气象传感网技术工程中心联合开放基金课题(KDXS1407;KDXS1504);江苏高校品牌专业建设工程资助项目(TAPP)~~

摘　　要：为了解决多个功能模块同时访问同一存储器单元而出现冲突问题,设计了带FIFO的多通道存储控制器。首先给出其工作原理以及系统架构设计,然后采用有限状态机和Verilog HDL语言设计各模块,并在ModelSim上完成前仿真和后仿真,最后在Xilinx FPGA平台上完成下板功能验证。实践表明该存储控制器在保证访问不冲突的前提下最大化了存储器访问效率,提供了简单易用的用户接口,且可根据具体应用自由定义通道数和各通道轮询时间等参数,从而实现了最高资源利用效率。A multi-channel FIFO memory controller is designed to solve the conflict problem occurring when multiple functional modules access the same memory unit simultaneously.The work principle of the controller and the architecture design of the system are given.The finite state machine(FSM)and Verilog HDL language are used to design various modules.The presimulation and post-simulation are completed by using the ModelSim.The board unloading function verification is completed on the Xilinx FPGA platform.The practical results show that the memory controller can maximize the memory access efficiency on the premise of ensuring no access conflicts occur,provide an easy-to-use user interface,and easily define parameters such as the number of channels and the polling time of each channel according to the specific application,thereby achieving the highest resource utilization rate.

关 键 词：FIFO 有限状态机 VERILOG HDL MODELSIM FPGA 存储控制器 轮询时间 资源利用率 

分 类 号：TN830.3[电子电信—信息与通信工程] TP302[自动化与计算机技术—计算机系统结构]