RISC-V处理器的低功耗模式设计  

Low Power Mode Design of RISC-V Processor

作　　者：胡志杰 HU Zhi-jie(College of Physics and Information Engineering,Fuzhou University,Fuzhou Fujian 350116)

机构地区：[1]福州大学物理与信息工程学院,福建福州350116

出　　处：《数字技术与应用》2019年第2期179-180,共2页Digital Technology & Application

摘　　要：本设计提出了一种基于RISC-V指令集架构的SOC低功耗模式设计。该设计适用于小型、移动的处理器芯片,以及对低功耗模式需求越来越高的人工智能应用芯片。本设计分为低频模式、睡眠模式、停机模式。本设计通过VCS+VERDI联调仿真,观察整体设计的波形,通过VIVADO软件对不同工作模式下的电路综合分析。经过计算,处理器在三种不同工作模式下的功耗分别降低了正常模式下的4%、8%、63%。在FPGA板的功耗测试中,睡眠模式下FPGA板整体功耗降低了正常模式下的19%功耗。This design presents a low power mode design of SOC based on RISC-V instruction set architecture.This design is suitable for small,mobile processor chips,and artificial intelligence application chips with increasing demand for low power mode.This design is divided into lowfrequency mode,sleep mode,shutdown mode.Through VCS+VERDI simulation,the design observes the waveform of the overall design,and comprehensively analyses the circuit under different working modes by VIVADO software.After calculation,the power consumption of the processor in three different working modes is reduced by 4%,8%and 63%respectively in the normal mode.In the power consumption test of the FPGA board,the overall power consumption of the board in sleep mode is reduced by 19%in normal mode.

关 键 词：时钟控制 低功耗 降频模式 睡眠模式 停机模式 

分 类 号：TP216[自动化与计算机技术—检测技术与自动化装置]