(25,20)线性分组编译码器设计及其FPGA实现  

Design of (25,20)linear block codec and its FPGA implementation

作　　者：李淑婧[1] 王蕾[1] 任宝祥[1] 李哲[1] 尚耀波[1] LI Shujing;WANG Lei;REN Baoxiang;LI Zhe;SHANG Yaobo(Air Force Engineering University,Xi’an 710051,China)

机构地区：[1]空军工程大学

出　　处：《现代电子技术》2019年第11期7-10,共4页Modern Electronics Technique

基　　金：国家自然科学基金(61401499);陕西省电子信息系统综合集成重点实验室资助项目~~

摘　　要：随着通信速率的提高,有噪信道的可靠通信通过信道编码来实现。文中设计的(25,20)线性分组编译码器结合汉明码能纠正一位错误且具有编码效率较高、译码电路简单、译码延时小等优点。分析伴随式与错误图样的对应关系,采用并行处理的方式,使用硬件描述语言VHDL在Xilinx公司的Vivado2016.1环境下编程实现。通过ModelSim仿真平台验证,降低了实现的复杂度。在工程实践中将编译码器加入某实测通信系统,实现了在Artix.7系列xc7z030fbg676.1的芯片上占用较少的硬件资源实现(25,20)线性分组编译码,提高系统传输的可靠性,验证了该设计的优良性能。With the increase of signal transmission speed,the reliable communication of noisy channel is realized by means of channel coding.The(25,20)linear block codec is designed,and combined with the advantages of Hamming code which can correct the error of one bit and has high encoding efficiency,simple decoding circuit and short decoding delay.The corresponding relationship between syndrome and error pattern is analyzed.The parallel processing mode and hardware description language VHDL are used for programming implementation in Vivado 2016.1 environment.The codec is verified with Modelsim simulation platform,and the simulation results show that the complexity is reduced.The(25,20)linear block codec is applied to a certain actual measurement communication system,which can realize the(25,20)linear block coding and decoding with little hardware resources on the chip xc7z030fbg676-1 of Artix-7 series,improve the system transmission reliability,and verify the excellent performance of the design.

关 键 词：信道编码 (25 20)线性分组码 汉明码 伴随式 错误图样 并行处理 

分 类 号：TN911.22-34[电子电信—通信与信息系统]