一种基于改进基4 Booth算法和Wallace树结构的乘法器设计  

A design of multiplier based on modified Booth-4 algorithm and Wallace tree

作　　者：吴美琪 赵宏亮[1] 刘兴辉[1] 康大为[1] 李威[2] WU Mei-qi;ZHAO Hong-liang;LIU Xing-hui;KANG Da-wei;LI Wei(School of Physics,Liaoning University,Shenyang 110036,China;Institute of ComputingTechnology,Chinese Academy of Sciences,Beijing 100190,China)

机构地区：[1]辽宁大学物理学院,辽宁沈阳110036 [2]中国科学院计算技术研究所,北京100190

出　　处：《电子设计工程》2019年第16期145-150,共6页Electronic Design Engineering

基　　金：辽宁省教育厅研究生教育教学改革联合培养项目(辽教函[2017]24号);2016年辽宁省博士科研启动基金指导计划项目(20161094)

摘　　要：以实现25×18位带符号快速数字乘法器为目标,采用改进的基4Booth算法以3位编码产生部分积,优化最低位产生电路,使用统一的操作扩展各部分积符号位,相比于传统方法提高了阵列规则性、节省了芯片面积;用传输门构成基本压缩器,并在此基础上优化实现高阶压缩器,进而组成一个Wallace树结构,同时将9组部分积压缩为2组,使电路仅需3级压缩、关键路径延迟时间为8个异或门延迟,有效地提高了压缩效率和降低了关键路径延迟时间。采用GF28nmCMOS工艺,以全定制流程设计,版图面积为0.0112mm^2,仿真环境标准电压1.0V、温度25℃、最高工作时钟频率1.0GHz,系统的功耗频率比为3.52mW/GHz,关键路径延时为636ps,组合逻辑路径旁路寄存器的绝对延时为1.67ns。A 25 × 18 bits signed digital multiplier is presented .Compared with the traditional method, the array regularity was improved and the area consumption was reduced by using the modified Booth-4 algorithm based on a 3 bits code generating partial product,optimizing least-significant bit generating circuit and employing uniform operations to extend the sign bit of each partial product. The transmission gates were used to form the basic compressors,and on this basis the high order compressors were optimally implemented. Composed of these compressors,the Wallace tree compressing 9 groups of partial product to 2 groups only needs three-stage compression and 8XOR-delay in critical path. With full- custom design in GF 28 nm CMOS process,the chip area is 0.0112 mm ^2 . The simulation results indicate that the power frequency ratio is 3.52 mW/GHz,the critical path delay is 636 ps,and the absolute delay of combinational logic path bypass registers is 1.67 ns at 1.0 V,25 ℃ and the highest frequency of 1.0 GHz.

关 键 词：乘法器 改进的基4Booth算法 部分积阵列 WALLACE树 压缩器 

分 类 号：TN432[电子电信—微电子学与固体电子学]