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作 者:张康 李婷 刘小洁 高跃昕 刘宜霖 ZHANG Kang;LI Ting;LIU Xiaojie;GAO Yuexin;LIU Yilin(The 45^th Research Institute of CETC,Beijing 100176,China)
机构地区:[1]中国电子科技集团公司第四十五研究所
出 处:《电子工业专用设备》2019年第4期1-4,64,共5页Equipment for Electronic Products Manufacturing
摘 要:TSV技术是实现集成电路3D封装互连、降低RC延迟和信号干扰、改善芯片传输速度及功耗的有效方法。基于TSV技术的CMP工艺主要用于通孔大马士革铜工艺淀积后的正面抛光和晶圆背面TSV结构的暴露及平坦化工艺,分步抛光工艺匹配技术具有去除速率高、抛光时间可控、碎片风险小、选择比低、凹陷及凸起缺陷少等特点,铜的去除率大于1000nm/min,铜凹陷小于15nm,平坦化表面粗糙度小于1nm,表面不均匀度小于5%,可满足TSV工艺技术中晶圆表面的平坦化需求。TSV technology is an effective method to realize 3D package interconnection, to reduce RC delay and signal interference, and to improve chip speed and power consumption. CMP is used for polishing Damascus copper deposited and the exposure and polishing of TSV structure on the backside of wafer. Appropriate process matching has the characteristics of high removal rate, long polishing time, low selection ratio, fewer dishing and extrusion. The removal rate of copper is more than 1 000 nm/min, dishing is less than 15 nm, the roughness is less than 1 nm, and the surface non-uniformity is less than 5%, which can meet CMP(Chemical mechanical planarization) requirements of TSV(Through Silicon Via) technology.
分 类 号:TN305.2[电子电信—物理电子学]
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