超大规模集成电路的板级测试研究  

Research on Plate-Level Test of VLSI

作　　者：李志威[1] 潘中良[2] 叶小敏 LI Zhiwei;PAN Zhongliang;YE Xiaomin(Aircraft Maintenance Engineering College, Guangzhou Civil Aviation College, Guangzhou 510800, China;School of Physics and Telecommunication Engineering, South China Normal University, Guangzhou 510006, China;Magneti Marelli Automotive Electronics( Guangzhou) Co.,Ltd., Guangzhou 510800, China)

机构地区：[1]广州民航职业技术学院飞机维修工程学院,广州510800 [2]华南师范大学物理与电信工程学院,广州510006 [3]马瑞利汽车电子(广州)有限公司,广州510800

出　　处：《重庆理工大学学报（自然科学）》2019年第9期170-175,共6页Journal of Chongqing University of Technology：Natural Science

基　　金：广东省科技计划项目(2016B090918071,2014A040401076);广州民航职业技术学院科研项目(17X0118)

摘　　要：为检测以超大规模集成电路为核心的电子设备,设计了基于边界扫描技术的电路测试系统。对超大规模集成电路进行板级测试,并提出在互连网络两端的边界扫描单元分别做输出操作的针对互连测试和簇测试过程的测试方法。测试结果表明:利用该方法,提高了超大规模集成电路板级故障的分辨能力,获得了更好的测试效果。In order to detect the electronic equipment with VLSI as the core,a set of circuit testing system based on boundary-scan technology was designed,the plate-level test of VLSI was carried out,and an effective test method for interconnection testing and cluster testing is proposed,in which the boundary scan units at both ends of the interconnection network were used for output. The test results showed that the test system by using this testing methods,improved the resolution of the plate-level fault of VLSI,and better test results was obtained.

关 键 词：超大规模集成电路 板级测试 互连测试 簇测试 

分 类 号：TN407[电子电信—微电子学与固体电子学]