基于神经网络的逻辑门NBTI退化建模与计算  

Modeling and Calculation for NBTI-Induced Degradation in Logic Gates Based on Neural Network Fitting

作　　者：卿健[1] 张珀菁 郭海霞 李小进[1] 孙亚宾 石艳玲[1] QING Jian;ZHANG Pojing;GUO Haixia;LI Xiaojin;SUN Yabin;SHI Yanling(Dept.of Electrical Engineering,East China Normal University,Shanghai 200241,P.R.China)

机构地区：[1]华东师范大学电子工程系

出　　处：《微电子学》2019年第5期713-717,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61574056,61204038)

摘　　要：提出了基于神经网络的逻辑门退化延迟模型。根据逻辑门延迟数据特征,采用神经网络BP算法,对仿真样本数据进行训练,获得7种基本逻辑门延迟退化计算方法以及网络模型参数。基于45nm CMOS工艺进行验证,模型计算值与Spice仿真数据的误差不超过5%。在此基础上,提出NBTI效应下的电路路径延迟退化计算流程,并编写计算程序,对基本逻辑门构成的任意组合逻辑电路(ISCAS85)进行NBTI退化分析,获得路径时序的NBTI退化量。采用该模型,可在电路设计阶段预测电路时序,为高性能、高可靠性数字集成电路的设计提供重要依据。A novel model of NBTI-induced delay degradation in logic gates based on the neural network fitting was proposed.On the basis of the characteristics of the delay data of logic gates,the BP algorithm was chosen.The simulation data from a large quantity of samples was generated to train and optimize the model.In this way,the aging aware models of seven fundamental logic gates had been built up.Based on 45nm CMOS technology,Spice simulation was used to verify the calculation data which came from the proposed model.The experimental result showed that the error between Spice simulation and model calculation was less than 5%.Furthermore,the calculation flow chart of delay degradation in timing analysis of logic circuits was discussed.With the proposed flow chart,the circuit(ISCAS85)which was composed of a few fundamental logic gates was taken as an example for timing analysis including the performance degradation caused by NBTI effect.The delay of all paths in ISCAS85was obtained to made the circuit degradation measurable.The NBTI modeling of delay degradation in logic gates could predict design margins without unwanted timing errors under NBTI-induced aging,which helped the aging-tolerant design in high performance digital VLSI circuits.

关 键 词：NBTI效应 逻辑电路 退化延迟模型 神经网络 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN432