基于IC互连线开路故障的Y/R模型  

Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections

作　　者：赵天绪[1] 郝跃[1] 马佩军[1] 

机构地区：[1]西安电子科技大学微电子所

出　　处：《电子学报》2002年第11期1707-1710,共4页Acta Electronica Sinica

基　　金：国家科技攻关项目 (No .96 738 0 1 0 3 1 0 )

摘　　要：在半导体制造业中 ,IC的成品率和可靠性 (Y/R)是倍受关注的两个问题 .研究表明它们之间存在着显著的相关性 .为了表征这种相关性 ,本文从缺陷造成互连线开路的机理出发 ,分析了成品率关键面积和可靠性关键面积 ,提出了IC成品率与可靠性关系模型 .通过模拟实验给出了该模型的有效性验证 .Yield and reliability are two problems that are focused on semiconductor manufacturing.The researched results show that there exists a relation between yield and reliability of IC's.In order to describe this correlativity,the yield critical area and the reliability critical area are analyzed based on the mechanism of open circuit of interconnections caused by manufacturing defects,and the model of relation between IC's yield and reliability is presented in this paper.Finally,the validity of this model is shown by computer simulation.

关 键 词：IC 互连线开路故障 Y/R模型 成品率 可靠性 关键面积 半导体制造业 集成电路 

分 类 号：TN406[电子电信—微电子学与固体电子学]