高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究  

The Electrical Mechanism Study of High-Ruggedness N-Channel RF-LDMOS Under TLP Stress

作　　者：李浩[1,2] 任建伟 杜寰[1] LI Hao;REN Jian-wei;DU Huan(Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《电子学报》2019年第11期2317-2322,共6页Acta Electronica Sinica

摘　　要：提高射频功率器件的鲁棒性有利于增强器件的抗静电放电能力和抗失配能力.为了直观地了解器件内部发生的电学过程,本文研究了高鲁棒性N型沟道RF-LDMOS (Radio Frequency Lateral Diffusion MOS)在TLP (Transmission Line Pulse)应力下的电学机理.利用0.18μm BCD (Bipolar/CMOS/DMOS)先进制程,实现了特定尺寸器件的设计与流片.通过实测与仿真的对比,发现静电放电失效的随机性、芯片内部的热效应是导致仿真和实测差异的非理想因素.通过对TLP仿真的各阶段重要节点的分析,证明了源极下方的P型埋层有利于提高空穴电流的泄放能力,从而提高RF-LDMOS的鲁棒性.Improving the ruggedness of radio frequency power device is beneficial to enhance the ability of withstanding electro-static discharge(ESD) and output mis-match.To understand the electrical process happened in device intuitively,the electrical mechanism of state-of-art high-ruggedness N-channel RF-LDMOS(Radio Frequency Lateral Diffusion MOS),under TLP(Transmission Line Pulse) stress,has been studied.RF-LDMOS FETs with different gate widths had been manufactured using advanced 0.18μm BCD(Bipolar/CMOS/DMOS) process.It is found that the different failure points of simulation and measurement are coming from the random failure of ESD stress and thermal problems.The simulation results of different nodes under TLP stress proved that the P buried layer under source area plays an important role in holes flowing,and improves the ruggedness of RF-LDMOS.

关 键 词：射频功率器件 LDMOS 芯片设计 BCD制程 TLP 碰撞电离 P型埋层 

分 类 号：TN386.4[电子电信—物理电子学]