基于DLL的3.5 GHz时钟校准电路设计  

Design of 3.5 GHz Clock Calibration Circuit Based On DLL

作　　者：杨俊浩 杨霄垒 张涛 苏小波 周骏 YANG Junhao;YANG Xiaolei;ZHANG Tao;SU Xiaobo;ZHOU Jun(China Key System&Integrated Circuit Co.,LTD.,Wuxi 214072,China)

机构地区：[1]中科芯集成电路有限公司

出　　处：《电子与封装》2019年第12期23-27,共5页Electronics & Packaging

摘　　要：设计了一种基于某65 nm CMOS工艺的3.5 GHz时钟校准电路,应用于高速高精度DAC中。该电路采用延迟锁相环结构,优化DAC内部的数字和模拟通路时钟信号,使数据在3.5 GHz速率下完成正确转换,有效提高了系统时钟的稳定性。电源电压为1.2 V/3.3 V,时钟相位调节精度为2 ps/LSB,目标锁定相位可调,带有时钟占空比调制功能,最大功耗小于60 mW。A 3.5 GHz clock calibration circuit of high speed and high precision DAC implemented in SMIC 65 nm CMOS is presented. The circuit includes a delay lock loop(DLL) to optimize the timing hand-off between the digital clock domain and the DAC core over temperature, time, and power supply variation, also to ensure correct data transfer with 3.5 GHz and improve the reliability of system clock. The proposed circuit is with 1.2 V/3.3 V dual power supply, 2 ps/LSB of the clock phase regulating precision, programmable target set-phase and the ability of clock duty cycle modulation. The largest power dissipation is lower than 60 mW.

关 键 词：时钟校准 延迟锁相环 数模转换器 占空比调制 

分 类 号：TN402[电子电信—微电子学与固体电子学]