改进的基于嵌入式SoC卷积神经网络识别模型  

IMPROVED CONVOLUTIONAL NEURAL NETWORK RECOGNITION MODEL BASED ON EMBEDDED SOC

作　　者：孙磊 肖金球[1,2] 夏禹 顾敏明[1,2] Sun Lei;Xiao Jinqiu;Xia Yu;Gu Minming(School of Electronics and Information Engineering,Suzhou University of Science and Technology,Suzhou 215009,Jiangsu,China;Intelligent Measurement and Control Engineering Technology Research Center,Suzhou University of Science and Technology,Suzhou 215009,Jiangsu,China)

机构地区：[1]苏州科技大学电子与信息工程学院,江苏苏州215009 [2]苏州科技大学苏州市智能测控工程技术研究中心,江苏苏州215009

出　　处：《计算机应用与软件》2020年第3期257-260,共4页Computer Applications and Software

基　　金：江苏省产学研前瞻性联合基金项目(BY2011132);江苏省研究生创新与教改项目(09150001)。

摘　　要：针对当前在FPGA上实现卷积神经网络模型时卷积计算消耗资源大,提高FPGA芯片性能代价较大等问题,提出一种改进的基于嵌入式SoC的优化设计方法。对卷积计算的实现方法和存储访问通道加以优化,以提高并行计算性能;将32位位宽的浮点数量化为16位定点数,加快前向传播的数据传输;结合硬件描述软件的高层次综合技术,将卷积神经网络映射到硬件平台成为一种同步数据流模型从而加快计算速度。通过实验证明,该方案较现有设计节约了89%的BRAM和72%的LUT,在工作频率为100 MHz的测试中,其处理速度比单独使用Cortex-A9的方案提升了42倍。Aiming at the problems that convolution computing consumes a lot of resources and costs a lot to improve the performance of the FPGA chip when implementing the convolutional neural network model on FPGA,we propose an improved design method based on embedded SoC.The implementation method and storage access channel of convolutional computing were optimized to improve the performance of parallel computation.Then,the 32-bit-wide floating-point number was quantified to 16-bit fixed-point number to speed up the data transmission of forward propagation.We combined the high-level synthesis technology of hardware description software,and the convolutional neural network was mapped to the hardware platform to become a synchronous data flow model to speed up the calculation speed.The experimental results show that the proposed optimization scheme saves 89%of BRAM and 72%of UT,compared with the existing design.The processing speed of the proposed scheme is 42 times faster than the scheme using Cortex-A9 alone in the 100 Mhz.

关 键 词：卷积神经网络 嵌入式系统 FPGA 定点数量化 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]