基于查表法的CRC算法实现与优化  

Design of Configurable Low Power CRC Computing Module

作　　者：王宁平 冯全源[1] WANG Ningping;FENG Quanyuan(Institute of Microelectronics of Southwest Jiaotong University,Sichuan,611756,China)

机构地区：[1]西南交通大学微电子研究所

出　　处：《集成电路应用》2020年第3期17-19,共3页Application of IC

基　　金：国家自然科学基金重点项目资助(61531016,61831017);四川省科技支撑计划重点项目资助(2018GZ0139);四川省重大科技专项项目资助(2018GZDZX0001)

摘　　要：基于数据传输系统带宽越来越大,数据传输过程中发生错误的概率也越来越高,设计用于检错和纠错的校验码产生模块是非常必要的。完成一种可配置的并行CRC运算模块的设计,数据长度和CRC运算版本皆可进行配置,在一个时钟周期内即可并行计算得到CRC校验结果。首先通过线性反馈移位寄存器实现了串行CRC计算模块,然后结合查表法多次例化串行CRC计算模块、并将上次运算结果作为本次运算的初值实现了可并行运算的CRC校验码计算模块。With the increasing bandwidth of data transmission systems, the probability of errors occurring during data transmission is also increasing, and it is very necessary to design a check code generation module for error detection and correction. The design of a configurable parallel CRC calculation module is completed. Both the data length and the version of CRC can be configured, and the CRC check result can be calculated in parallel during one clock cycle. First, the serial CRC calculation module was implemented by a linear feedback shift register, and then the serial CRC calculation module was instantiated multiple times in combination with the table lookup method, and the previous calculation result was used as the initial value of this calculation to implement a parallel operation CRC check code calculation module.

关 键 词：集成电路设计 循环冗余校验CRC运算 线性反馈移位寄存器 可配置 VERILOG 查表法 寄存器验证 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN791