应用于10Gbase-KR的二阶时钟数据恢复电路的建模分析与电路设计  

Modeling analysis and circuit design of second-order clock data recovery circuit applied to 10 Gbase-KR

作　　者：栾文焕 王登杰 贾晨 王自强[1] LUAN Wen-huan;WANG Deng-jie;JIA Chen;WANG Zi-qiang(Institute of Microelectronics,Tsinghua University,Beijing 100084,China;Research Institute of Tsinghua University in Shenzhen,Shenzhen 518057,China)

机构地区：[1]清华大学微电子学研究所,北京100084 [2]深圳清华大学研究院,深圳518057

出　　处：《微电子学与计算机》2020年第3期1-4,共4页Microelectronics & Computer

基　　金：深圳市科技创新委员会支持(JSGG20170413153845042)。

摘　　要：本文针对10 Gbase-KR的应用场合,设计了一款基于相位插值器的二阶CDR,通过对其进行线性建模分析,折中抖动容忍、锁定时间以及抖动峰值的关系,选取合适的增益系数,并采用SMIC 40 nm CMOS工艺完成了电路设计.其中二阶滤波器的比例和积分系数可调,可以追踪1000 ppm的偏差,恢复时钟的抖动最差情况为24 ps.In this paper,a second-order CDR based on phase interpolator is designed for 10 Gbase-KR.Through linear modeling and analysis,it makes a compromise between jitter tolerance,lock-in time and jitter peak value,and the appropriate gain coefficient is selected.The circuit is designed by SMIC 40 nm CMOS process,in which the ratio and integral coefficient of the second-order filter can be adjusted to track the deviation of 1000 ppm,and the worst case of recovery clock jitter is 24 ps.

关 键 词：高速串行 接收机 时钟数据恢复 二阶滤波器 

分 类 号：TN492[电子电信—微电子学与固体电子学]