深亚微米SOI工艺SoC设计中天线效应的消除  

Elimination of Process Antenna Effect in Deep-submircon SOI SoC Design

作　　者：王淑芬 史冬霞 桂江华 WANG Shufen;SHI Dongxia;GUI Jianghua(China Key System Co.,Ltd.,Wuxi 214072,China)

机构地区：[1]中科芯集成电路有限公司,江苏无锡214072

出　　处：《电子与封装》2020年第4期53-57,共5页Electronics & Packaging

摘　　要：深亚微米SOI片上系统芯片(SoC)因其工艺特性,按照常规的布局布线(PNR)流程,出现了约一万个天线效应违规。介绍了一种在布局布线阶段不插入反偏二极管就可以消除大量天线效应违规的优化迭代流程。通过对天线效应的产生以及天线比率公式的分析,从线长和栅面积角度考虑天线效应的修复,结合自动布局布线设计工具SoC Encounter对这些因素的控制,可以在布局布线阶段消除天线效应的违规,并能与版图验证的结果保持一致。在一款通用抗辐照SoC芯片的设计中,应用该优化流程在布局布线阶段消除了设计中的天线效应违规,有效节约了芯片整体设计时间。With normal PNR(place and route)flow,there will be about ten thousand PAE(process antenna effect)violations in deep-submircon SOI SoC design.A new optimized interation flow for completely eliminate PAE combined without using reverse-biased diode in PNR stage was presented.Through the analysis of the PAE generated and the antenna ratio formula,the length and gate area of the metal can be considered to repair the PAE.Through the PNR tool to control these factor,PAE can be eliminated combined in PNR stage.This optimized flow was used in general radiation hardened SoC chip design,with the elimination in the PNR stage,and the design time is saved as well.

关 键 词：SOI工艺 天线效应 天线规则 布局布线 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]