28nm NMOSFET器件漏电的研究与优化  

Mechanism and Optimization of 28 nm NMOSFET Device Leakage

作　　者：勾鹏 王海涛 周晓君 刘巍 田明 GOU Peng;WANG Haitao;ZHOU Xiaojun;LIU Wei;TIAN Ming(Shanghai Huali Integrated Circuit Corporation,Shanghai,201314,China)

机构地区：[1]上海华力集成电路制造有限公司,上海201314

出　　处：《集成电路应用》2020年第5期31-33,共3页Application of IC

基　　金：上海市经济和信息化委员会软件和集成电路产业发展专项基金(1500204)。

摘　　要：随着MOSFET器件尺寸不断缩小,短沟道器件的漏电越来越严重,导致芯片的发热现象更严重,极大降低了芯片的可靠性。基于HLMC 28 nm低功耗逻辑平台,研究了轻掺杂漏(LDD)流程中离子注入工艺条件对NMOSFET器件漏电的影响及物理机制。实验结果表明,通过优化口袋及预非晶化离子注入条件,可以显著改善器件漏电。同时借助半导体工艺及器件仿真工具TCAD,进一步研究了NMOSFET器件的漏电机理,与实验结果得到了很好的吻合。With the shrinking size of MOSFET devices,the leakage of short-channel devices is more and more serious,leading to more serious chip heating phenomenon,which greatly reduces the reliability of the chip.Based on HLMC 28 nm Low Power logic platform,we studied the influence and mechanism for NMOS device leakage by the optimization of LDD implant.The experimental results show that by optimizing the conditions of pocket and amorphous ion implantation,leakage can be significantly improved.At the same time,the leakage mechanism of NMOSFET device is further studied with the help of semiconductor process and device simulation tool TCAD,which is in good agreement with the experimental results.

关 键 词：集成电路制造 NMOSFET 器件 漏电 LDD离子注入 

分 类 号：TN405[电子电信—微电子学与固体电子学]