130 nm加固SOI工艺的抗辐射控制芯片设计  

Design of radiation-tolerant controller chip in 130 nm hardened SOI process

作　　者：常永伟 余超 刘海静[1] 王正 董业民[1,2] CHANG Yongwei;YU Chao;LIU Haijing;WANG Zheng;DONG Yemin(State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;University of Chinese Academy of Sciences, Beijing 100049, China)

机构地区：[1]中国科学院上海微系统与信息技术研究所,信息功能材料国家重点实验室,上海200050 [2]中国科学院大学,北京100049

出　　处：《国防科技大学学报》2020年第3期17-21,共5页Journal of National University of Defense Technology

基　　金：中科院重点部署资助项目(KGFZD-135-16-015)。

摘　　要：针对航天电子系统控制模块对集成电路的抗辐射需求,在130 nm部分耗尽绝缘体上硅(Silicon-On-Insulator,SOI)工艺平台上设计了一款基于比例、积分、微分控制算法的控制芯片,并分别从晶圆材料、制备工艺、版图设计的角度对芯片进行了总剂量辐射加固。流片测试结果表明,芯片的调节精度达到了5×10-12,与进口抗辐射现场可编程门阵列水平相当;在长时间频率稳定度方面,芯片优于国外抗辐射现场可编程门阵列。对芯片进行的模拟辐照试验表明,芯片在300 krad(Si)的总剂量辐照条件下依然可以正常工作。Aimed at the anti-radiation requirements of the aerospace electronic system control module for integrated circuits,a controller chip based on the proportion,integral and differential algorithms was designed on a 130 nm partially depleted SOI(silicon-on-insulator)process platform.The TID(total ionizing dose)radiation reinforcement was investigated in terms of SOI wafer,fabrication process and layout design,respectively.The test results of the chip show that the adjustment accuracy of the chip reaches 5×10-12,which is equivalent to the imported radiation-tolerant FPGA(field programmable gate array);the chip is superior to the foreign anti-radiation FPGA in terms of long-term frequency stability.TID experiments were carried out and the results show that the chip can function normally under the total dose of 300 krad(Si).

关 键 词：集成电路 抗辐射 绝缘体上硅 控制芯片 

分 类 号：TN492[电子电信—微电子学与固体电子学]