基于贝叶斯网络的验证激励向量生成研究  

Research on Generation of Verification Incentive Vector Based on Bayesian Network

作　　者：王润 蒋剑飞[1] 王琴[1] WANG Run;JIANG Jian-fei;WANG Qin(Microelectronics Institute,Shanghai Jiao Tong University,Shanghai 200240,China)

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《软件导刊》2020年第7期1-4,共4页Software Guide

基　　金：国家自然科学基金项目(61176037)。

摘　　要：为了解决传统数字芯片验证环节中基于仿真的验证(或动态验证)功能覆盖率收敛速度慢的缺点,提出一种新的以功能覆盖为导向的测试用例生成方法,该方法基于贝叶斯网络和机器学习技术,可实现从覆盖模型到测试用例生成器反馈回路的自动关闭,在DUT的验证过程中,使用该方法为所测试的设计生成新的激励。实验结果表明,基于贝叶斯网络的CDG技术测试用例使用较少,覆盖率收敛更快,与传统基于仿真的验证技术相比,测试用例数量减少了43%。基于贝叶斯网络的CDG技术提高了覆盖率的收敛速度,缩短了验证周期,相比于传统动态验证技术而言其芯片功能验证更完善。In order to solve the problem of slow convergence rate of functional coverage of simulation based verification(or dynamic verification)in the traditional verification of digital chips,this paper proposes a new method of test case generation based on function coverage.Based on Bayesian network and machine learning technology,this method provides an effective method to automatically close the feedback loop from coverage model to test case generator.In the verification process of DUT(design under test),this method is used to generate new incentives for the tested design.The experimental results show that the CDG(coverage driven test case generation)technology based on Bayesian network uses fewer test cases,and the coverage convergence is faster.Compared with the traditional simulation based verification technology,the number of test cases is reduced by 43%.CDG technology based on Bayesian network improves the convergence rate of coverage and reduces the verification cycle.Compared with the traditional dynamic verification technology,the chip function verification is more complete.

关 键 词：功能验证 贝叶斯网络 机器学习 CDG 覆盖率 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]