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作 者:焦芳[1] 陈金远[1] JIAO Fang;CHEN Jinyuan(Nanjing Electronic Devices Instituty Nanjing,210016,CHN)
出 处:《固体电子学研究与进展》2020年第3期169-172,共4页Research & Progress of SSE
摘 要:采用栅长为0.25μm的增强型pHEMT工艺设计并制造了一款新型达林顿放大器芯片。该达林顿放大器第二级采用了共源共栅结构,引入了负反馈,并采用了有源偏置。在0.1~6.0 GHz范围内,小信号增益大于23dB,平坦度小于±1 dB,驻波小于2,噪声系数小于1.5 dB,输出1 dB压缩点大于21 dBm,输出三阶交调截断点大于34 dBm@1.8 GHz。所设计的共源共栅达林顿放大器具有较好的带宽和一致性等优点,适用于4G、5G通信系统以及雷达收发组件等。A new type of Darlington amplifier chip with gate length of 0.25 μm was designed and fabricated by using the enhanced pHEMT process. This type of Darlington amplifier had cascode structure in the second stage,the negative feedback was introduced,and the active bias was used. In the range of 0.1~6.0 GHz,the small signal gain is greater than 23 dB,the flatness is less than ±1 dB,the VSWR is less than 2,the noise figure is less than 1.5 dB,and the output compression point of 1 dB is greater than 21 dBm,and the output third-order intermodulation cutoff point(OIP3)is greater than 34 dBm@1.8 GHz. The cascode Darlington amplifier designed in this paper has better bandwidth and equalization. It is suitable for 4 G,5 G communication systems and radar transceiver components.
分 类 号:TN722.5[电子电信—电路与系统]
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