一种面向多处理器互连的高速串行传输系统设计  

Design of high speed serial transmission system for multiprocessor interconnects

作　　者：许晋彰 景乃锋 蒋剑飞[1] XU Jin-zhang;JING Nai-feng;JIANG Jian-fei(School of Electronic Information and Electrical Engineering,Shanghai Jiao TongUniversity,Shanghai 200240,China)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240

出　　处：《微电子学与计算机》2020年第8期16-20,26,共6页Microelectronics & Computer

基　　金：国家自然科学基金项目(61176037)。

摘　　要：为了应对大数据量实时处理,解决处理器间通信带宽瓶颈.采用自主设计的混合多FPGA平台搭建了面向新型RISC-V处理器互连的高速串行传输系统,通过对互连接口的改进,实现了单通道4倍传输速率的提升.实验表明,该系统总吞吐率可达300 Gbps,单通道速率最高可达25 Gbps,支持的互连链路大于40路,传输误码率低于1E-11,能够满足高带宽、高可靠性传输需求,同时极大地减少了IO管脚数量.最后,基于该系统,在相同速率下对比和评估了3种高速串行协议的实现情况,为传输效率提升和系统优化提供帮助.In order to deal with the real-time processing of large data volume,and to solve the communication bandwidth bottleneck between processors,a high-speed serial transmission system for the interconnection of new RISC-V processors was built by self-developed hybrid multi-FPGA platform.It has achieved a single-channel 4 x transmission rate improvement.Experiments show that the total throughput rate of the system can reach 300 Gbps,the single channel rate can reach 25 Gbps,the supported interconnect links are greater than 40,and the transmission error rate is less than 1 E-11,which can meet most high-bandwidth and high-reliability transmission requirements,greatly reducing the number of IO pins.Finally,based on this system,at the same rate,compare and evaluate the implementation of three high-speed serial protocols,To help improve transmission efficiency and system optimization.

关 键 词：高速串行 多处理器互连 FPGA设计 片间通信 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]