一种基于40nm CMOS工艺的超宽带高速ADC  

An Ultra-Wideband High Speed ADC Based on 40 nm CMOS Process

作　　者：易政 郭轩 郑旭强 周磊[1] 季尔优 吴旦昱[1] Yi Zheng;Guo Xuan;Zheng Xuqiang;Zhou Lei;Ji Eryou;Wu Danyu(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;School of Electronic,Electrical and Communication Engineering,University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学电子电气与通信工程学院,北京100049

出　　处：《半导体技术》2020年第8期586-591,共6页Semiconductor Technology

基　　金：国家重点研发计划资助项目(2018YFB2202302)。

摘　　要：设计并实现了一款超宽带高速模数转换器(ADC)芯片。该ADC采用时间交织的架构,提高了数据转换的速率;改进了前端接收电路,增加了信号的模拟输入带宽;使用优化的自举开关电路以增加信号采样率;并通过高速的自校准比较器,校准比较器的输入失调电压,保证信号量化的速度。基于40 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该ADC芯片采样率可达36 GS/s,3 dB带宽可达18 GHz,且在模拟输入信号的全频带内,有效位数(ENOB)可达2.5 bit以上。该芯片可以对DC^18 GHz内的射频信号直接采样,简化超宽带接收机的结构,满足超宽带接收系统的应用需求,具有系统结构简单、成本低、集成度高的优点。An ultra-wideband high speed analog-to-digital converter(ADC)chip was designed and fabricated.A time-interleaved architecture was adopted to increase the data conversion rate.The front-end receiving circuit was improved to increase the analog input bandwidth of the signal.The optimized bootstrapped switch circuit was utilized to increase the signal sampling rate.The high speed self-calibrating comparator was adopted to calibrate the input offset voltage,which ensured the signal quantization speed.The ADC was designed and implemented based on 40 nm CMOS process.The test results show that the sampling rate of the ADC chip can reach 36 GS/s,the 3 dB bandwidth can reach 18 GHz and the effective number of bits(ENOB)can reach more than 2.5 bit in the full band of the analog input.This chip can directly sample the RF signal in DC-18 GHz,simplify the structure of the ultra-wideband receiver and satisfy the application requirements of the ultra-wideband receiving system.It has the advantages of simple system structure,low cost and high integration.

关 键 词：模数转换器(ADC) 时间交织 高采样率 自校准比较器 自举开关 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN792